The final specifications for the upcoming DDR5 memory: capacities up to 128GB and data transfer rate of up to 6.4Gbps!

According to anandtech , JEDEC (Solid State Technology Association that publishes industry standards for microelectronics including DDR memory) has released the standard final specification for upcoming DDR5 SDRAMs. The DDR5 standard increases the power and performance of DDR memory, doubling the maximum memory speeds while also increasing memory sizes significantly. It is expected that the new devices will be launched from the new standard in 2021 at the server level, before being released to computers and other devices at a later time. The primary focus of the DDR5 standard is to improve memory density and speed. And provide speeds up to 6.4Gbps and capacities up to 128GB.

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DDR5 memory compared to its predecessors

DDR5 DDR4 DDR3 LPDDR5
Slide (Die) density is maximumMax Die Density 64 Gbit 16 Gbit 4 Gbit 32 Gbit
Maximum UDIMM memory capacityMax UDIMM Size (DSDR) 128 GB 32 GB 8 GB N / A
Max Data RateMaximum data transfer rate 6.4 Gbps 3.2 Gbps 1.6 Gbps 6.4Gbps
ChannelsChannels 2 1 1 1
Total Width
(Non-ECC) Memory width
64-bits
(2 x 32-bit)
64-bits 64-bits 16-bits
Banks
(Per Group) Number of Volumes (per Group)
4 4 8 16
Bank GroupsThe number of storage groups 8/4 4/2 1 4
Burst Length BL16 BL8 BL8 BL16
Voltage (Vdd) 1.1v 1.2v 1.5v 1.05v
Vddq 1.1v 1.2v 1.5v 0.5v

Dense memories, larger stings

Compared to the previous DDR4 standard, this is the most obvious consumer change. DDR5 is designed with standards that will enable you to buy memory with a memory of up to 64 GB which is 4 times higher than the capacity of DDR4 memory of 16 GB. Of course, at first we will not see high-capacity memories, as the capabilities of the manufacturers do not allow this. While the speed improvements from DDR5 will be immediate, the capacity improvements will be incremental as manufacturers’ manufacturing intensity improves.

Presentation of JEDEC DDR5. Source anandtech .

Faster speed

Important new in DDR5 is increased memory bandwidth. JEDEC is looking to start things up a lot more aggressively than usual for this DDR memory spec. Usually a new standard shifts out of the way of its predecessor, just as it did with the transition from DDR3 to DDR4, where DDR3 stopped at 1.6Gbps and DDR4 started from there. But for DDR5, JEDEC aims much higher, with the group expecting to launch at 4.8Gbps, which is 50% faster than the top speed of DDR4’s 3.2Gbps. In the coming years, the current standard of specification will allow data rates of up to 6.4 Gbps, doubling the peak for DDR4.

The big change here is that similar to what we’ve seen in other standards like LPDDR4 and GDDR6, one DIMM is split into two channels. Instead of one 64-bit data channel per DIMM, DDR5 will offer two independent data channels of 32 bits per DIMM (or 40 bits in the case of an ECC). Meanwhile, the burst length of each channel is doubled from 8 bytes (BL8) to 16 bytes (BL16), which means that each channel will deliver 64 bytes per process. Compared to a DDR4 DIMM, a DDR5 DIMM operating at twice the rated memory speed (identical base speeds) will deliver two 64-byte processes the time it takes for a DDR4 DIMM to deliver a single process, doubling the effective bandwidth.

Generally, 64 bytes remain the magic number for memory processes since this is the standard size for the cache line. The larger burst length on DDR4 could have resulted in 128 bytes, which is too large for a single cache line, and would have resulted in efficiency losses if the controller had not sent a two-line value of concatenated data. By comparison, since the two DDR5 channels are independent, the memory controller can request 64 bytes from separate locations, making it more suitable for how the processors actually work and avoiding the efficiency penalty.

Fast vectors

Finding ways to increase the amount of parallelism within the DAMM memory and increase bus speed is more difficult: the idea is simple in concept and harder to implement. To double DDR memory speeds, the DDR5 bus must operate at twice the rate of DDR4.

To achieve this there are many changes to DDR5, but surprisingly there aren’t any major and fundamental changes to the memory bus like QDR or differential signalling. Instead, JEDEC managed to hit their targets with a slightly modified version of the DDR4 bus but with stricter operating conditions.

Simpler Motherboards, More Complex DIMMs: Voltage Regulation on DIMMs.

Along with fundamental changes in density and memory speeds, DDR5 also improves the operating voltage of DDR memory. DDR5 will work with a Vdd from 1.1v, down from 1.2v for DDR4. This should improve memory energy efficiency for DDR4.

The DDR5 standard also includes a fairly important change in how DIMM voltage is regulated. In short, responsibility for voltage regulation is transferred from the motherboard to the DIMM, which makes the DIMMs responsible for their voltage regulation needs. This means that DIMMs will now include a built-in voltage regulator, and this applies to everything from UDIMMs to LRDIMMs.

According to JEDEC, regulators integrated with DIMMs will also allow better overall voltage tolerance, improving DRAM throughput and also reducing DDR5’s power consumption relative to DDR4.

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Motherboard: a brief guide to its components and functions.

DDR5 DIMMs will have 288 pins, but with changes to the ports

DDR5 will retain the same number of 288 pins as DDR4. This is analogous to the transition from DDR2 to DDR3, in which the number of 240 pins is preserved.

However, DIM5 DIMMs cannot be used in DDR4 ports. Whereas, the command and address bus was shrunk and partitioned, with some copper reallocated to a second memory channel data bus. Instead of a single 24-bit CA bus, DDR5 will contain two 7-bit CA buses per channel. 7 is much less than half of the old bus, so things got more complicated for memory controllers in return.

Samples will be taken, and accreditation will begin in the next 12-18 months

With the announcement of the specifications and standards from JEDEC for ddr5 memory, the availability of memory manufactured with this standard has become closer. The major memory manufacturers who have been involved in DDR5 development from the start have already developed DIMMs and are now preparing to bring their first commercial devices to the market.

The overall adoption curve for DDR5 is expected to be similar to earlier DDR standards. This means that JEDEC expects DDR5s to start appearing in hardware within 12 to 18 years, and the group also expects the server market to once again be the driving force behind the early adoption of the new standard.

DDR5 is expected to have a longer life, if not slightly longer, as DDR4. DDR3 and DDR4 have had approximately seven years of life cycle, and DDR5 should have the same degree of stability.

In any case, major memory manufacturers are expected to begin rendering their prototypes and commercial DIMMs with the announcement of the DDR5 standard. With adoption beginning in earnest in 2021. It looks like the next year will bring some interesting changes to the markets.